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Overview
Google is hiring a Senior Design Engineer to work on custom circuits and SRAMs. You'll leverage your expertise in circuit design and physical design to drive cutting-edge TPU technology. This position requires 5+ years of experience in circuit design and scripting skills in Python and Tcl.
Job Description
Who you are
You have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. With 5 years of experience in Circuit Design, Physical Design (RTL-to-GDS), or Technology Development, you are well-versed in advanced nodes such as 7nm or below. Your experience includes concurrent optimization across custom circuit/IP and physical design, including Place and Route (PNR) and Static Timing Analysis (STA).
You possess a strong background in SPICE and transistor level design in advanced nodes, along with a solid understanding of CMOS device physics, finfet/GAA/nanosheet architectures, and layout parasitics. Your scripting and automation skills using Tcl and Python (or Perl) are well-developed, allowing you to streamline processes effectively. You may also hold a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
With 10 years of experience delivering optimized custom circuits, memories, IPs, and PNR blocks for product tapeout, you have a comprehensive understanding of major foundry technology files (PDKs), standard cell libraries, metal stacks, and other features. Your knowledge extends to characterization and verification of standard cells/SRAMs/register files, including power, noise, variation, and IR analysis. You excel in documentation and presentation skills, enabling you to communicate efficiently with teammates and vendors/partners.
What you'll do
In this role, you will shape the future of AI/ML hardware acceleration by driving and supporting test chip design, execution, and validation of critical circuit IPs. You will design and build custom circuits at the transistor and gate levels to support physical design and power-performance-area optimization. Your contributions will be pivotal in developing a leading-edge technology platform for custom, high-performance ASICs and SoCs, from design through manufacturing, packaging, and test.
You will collaborate closely with cross-functional teams to ensure that the designs meet performance and reliability standards. Your role will involve optimizing designs for power, area, and performance, ensuring that the final products are ready for tapeout. You will also be responsible for mentoring junior engineers and fostering a collaborative environment that encourages innovation and excellence.
What we offer
At Google, you will be part of a dynamic team that is at the forefront of technology. We offer competitive compensation and benefits, along with opportunities for professional growth and development. You will have access to cutting-edge resources and tools, enabling you to push the boundaries of what is possible in hardware design. Join us in making a significant impact in the world of AI and machine learning.
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