Front End Engineer • Mid-Level

Who you are

You hold a minimum of a BSc in Electrical Engineering and have a strong foundation in Verilog and/or System Verilog, along with proficiency in scripting languages. Your experience includes physical synthesis, particularly in logic and PPA optimisation techniques, which are crucial for delivering high-quality netlists. You have a solid understanding of physical design principles and static timing analysis, enabling you to contribute effectively to the GPU Front End Implementation team. Familiarity with DFT insertion and concepts across RTL and Gate-Level design is also part of your skill set. You thrive in collaborative environments, working closely with RTL and Physical design teams to achieve common goals.

What you'll do

In this role, you will be responsible for PPA optimisation of the netlist, ensuring that the GPUs you help create meet the highest standards of performance and efficiency. You will collaborate with various teams, including RTL and Physical design, to deliver key netlist quality milestones for your partition. Your contributions will directly impact the development of outstanding GPUs that enhance the user experience across Apple's product range. You will also be involved in understanding and improving current methodologies, helping to chart the future of Apple Silicon. Your role will require you to engage in problem-solving and innovative thinking, pushing the boundaries of what is possible in GPU design.

What we offer

Apple provides a dynamic work environment where innovation is at the forefront. You will have the opportunity to work on cutting-edge technology that impacts millions of users worldwide. The company values collaboration and encourages employees to bring their unique perspectives to the table. Apple is committed to fostering a diverse and inclusive workplace, ensuring that all employees feel valued and supported. You will be part of a team that is dedicated to excellence and driven by a shared passion for technology and design.