Tech Jobs

Graphcore • Bengaluru - On-Site

Graphcore is hiring a Silicon Logical Design Engineer to work within the logical design team, responsible for delivering high-quality microarchitecture and RTL for Graphcore chips. You'll work with technologies like C, C++, and Verilog in Bengaluru.

Apple • Santa Clara - On-Site

Apple is seeking a Standard Cell Design Methodology & Flow Engineer to contribute to cutting-edge processor design. You'll work with Verilog and SystemVerilog, applying machine learning techniques to enhance circuit performance. This role requires a strong background in digital design engineering.

Google • Taipei - On-Site

Google is hiring a Senior Silicon Bring Up and Test Manager to lead the development of custom silicon solutions. You'll work with ASIC and SoC design, utilizing EDA tools and DFT techniques. This position requires 8 years of experience in the field.

Google • Sunnyvale - On-Site

Google is hiring an RTL Design Engineer to work on Cloud TPU technology. You'll design and debug ASIC RTL using SystemVerilog or Verilog, and collaborate with physical design teams. This position requires experience in ASIC design and scripting languages.

Google • Fremont - On-Site

Google is hiring a Senior Test and Validation Engineer to lead custom silicon bringup and validation efforts. You'll work with Verilog and SystemVerilog, focusing on DFT techniques and silicon validation. This position requires 10 years of experience in custom silicon design.

Google • Sunnyvale - On-Site

Google is hiring an ASIC Design Engineer to work on ML accelerators. You'll design and verify complex digital designs, focusing on TPU architecture. This position requires 2+ years of experience in RTL design and proficiency in Verilog or SystemVerilog.

Amazon • Austin - On-Site

Amazon is hiring a Senior DFT Design Engineer to design and optimize hardware for AWS Machine Learning servers. You'll work with Verilog and System Verilog to develop state-of-the-art DFT architectures. This position requires 5+ years of practical DFT experience with complex SoC designs.

Apple • Munich - On-Site

Apple is hiring a SoC DFT Verification Engineer to lead pre-silicon verification efforts for their SoC products. You'll work with Verilog and scripting to develop test plans and validate IP. This position requires a strong background in verification methodologies.

Google • Austin

Google is hiring a CPU RTL Engineer to develop custom silicon solutions that power innovative products. You'll work with Verilog, SystemVerilog, and microprocessor architecture. This position requires 4 years of experience in digital logic design.

Google • Bengaluru

Google is hiring a Senior ASIC RTL Engineer to develop custom silicon solutions for their products. You'll work with Verilog, SystemVerilog, and ASIC design methodologies. This position requires 8 years of experience in digital logic design.

Apple • San Diego - On-Site

Apple is hiring a Mixed-Signal IP Firmware Engineer to develop firmware for critical features in SOCs. You'll work with C and ARM CPUs, focusing on post-silicon bringup and validation. This position requires 3+ years of relevant experience.

Google • Bengaluru - On-Site

Google is hiring a Staff Silicon Digital Design Engineer to develop custom silicon solutions that power innovative products. You'll work with Verilog and System Verilog, focusing on design and verification processes. This position requires 10 years of experience in electrical engineering or a related field.

Google • Bengaluru

Google is hiring a Silicon RTL Design Engineer to shape the future of AI/ML hardware acceleration. You'll work with programming languages and design tools to drive Tensor Processing Unit (TPU) technology. This position requires a PhD in a relevant field and experience in silicon engineering.

Apple • Linz - On-Site

Apple is seeking a Cellular IP Design Engineer to develop customized hardware IPs for digital signal processing. You'll collaborate with various teams to ensure optimal performance in Apple devices. This role requires experience in ASIC or FPGA designs and knowledge of signal processing principles.

Apple • Austin - On-Site

Apple is hiring an ASIC Design Engineer to design and integrate interconnect fabrics into SoCs. You'll work closely with multi-disciplinary teams and require expertise in RTL development and interconnect architectures. This position requires a minimum of 3 years of relevant industry experience.

Apple • Munich - On-Site

Apple is hiring a Cellular IP Design Engineer to develop customized hardware IPs for digital signal processing. You'll work closely with cross-functional teams to integrate IPs into SoCs. This role requires experience in ASIC or FPGA designs and knowledge of signal processing principles.

Apple • Cupertino - On-Site

Apple is hiring a Senior Firmware Engineer to develop firmware for mixed-signal IPs within SOCs. You'll work with C and assembly language, focusing on post-silicon bringup and validation. This role requires 10+ years of relevant experience.

Apple • Munich

Apple is hiring an Entry-Level DFT Engineer to contribute to System-on-Chip design efforts. You'll work with DFT specifications and tools like Verilog and VHDL in Munich.

Apple • Munich - On-Site

Apple is hiring an Experienced DfT Engineer to contribute to the design of future generations of revolutionary products. You'll work with technologies like Verilog and JTAG in a hands-on development team based in Munich.

Google • Bengaluru

Google is seeking a Senior ASIC RTL Engineer to integrate and automate flows of sub-systems and component IPs. You'll work with Verilog, SystemVerilog, and various scripting languages to optimize designs. This role requires 8+ years of experience in digital logic design.

Apple • California - On-Site

Apple is hiring a Senior Electrical Engineer specializing in DDR Mixed-Signal Circuit Design. You'll work on high-performance PHY designs and collaborate with various teams to deliver innovative products. This role requires significant experience in Analog/Mixed-Signal Circuit Design.

Optiver • Amsterdam - On-Site

Optiver is seeking an FPGA Engineer to design and implement hardware-based trading systems. You'll work closely with Traders and Software Engineers, utilizing skills in VHDL, Verilog, and SystemVerilog. This role requires experience in FPGA design and development.

Google • Haifa

Google is seeking a Senior Design Engineer for Google Cloud Networking to architect networking ASICs and develop RTL for ASIC subsystems. You'll work with C++, Python, and various hardware description languages. This role requires 8 years of experience in networking design.

Google • Sunnyvale - On-Site

Google is seeking a Physical Design Engineer, University Graduate, PhD to contribute to the design and closure of custom silicon solutions for AI/ML hardware acceleration. You'll work with technologies like Python, Verilog, and various physical design principles. This entry-level position is based in Sunnyvale, CA.

Google • Sunnyvale - On-Site

Google is seeking an RTL Design Engineer to contribute to the development of cutting-edge TPU technology for AI/ML applications. You'll work with Verilog and SystemVerilog in Sunnyvale, CA. This role requires a PhD in a relevant field and experience with RTL coding.