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- Over 100,000 employees globally
- Headquartered in Mountain View, California
- Parent company Alphabet Inc. valued at $1.5 trillion
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Google LLC, headquartered in Mountain View, California, is a global leader in internet-related services and products, including its flagship search engine, Google Search, and the Android operating system. With over 100,000 employees, Google also offers cloud computing services through Google Cloud P...
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Overview
Google is seeking a Senior Design Engineer for Google Cloud Networking to architect networking ASICs and develop RTL for ASIC subsystems. You'll work with C++, Python, and various hardware description languages. This role requires 8 years of experience in networking design.
Job Description
Who you are
You hold a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or possess equivalent practical experience. With 8 years of experience architecting networking ASICs from specification to production, you have a strong background in developing RTL for ASIC subsystems. Your expertise includes micro-architecture, design, verification, logic synthesis, and timing closure. You have experience working with design networking principles such as Remote Direct Memory Access (RDMA) or packet processing, focusing on low latency, high throughput, security, and reliability. You are familiar with architecting networking switches, endpoints, and hardware offloads, and have collaborated with software teams to optimize the hardware/software interface. Proficiency in a procedural programming language such as C++, Python, or Go is essential, along with knowledge of TCP, IP, Ethernet, PCIE, and DRAM. Familiarity with Network on Chip (NoC) principles and protocols like AXI, ACE, and CHI is a plus.
What you'll do
In this role, you will be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide, shaping the next generation of hardware experiences to deliver unparalleled performance, efficiency, and integration. Your responsibilities will include RTL development, coding and debugging in Verilog, SystemVerilog, and VHDL, as well as function and performance simulation debugging. You will participate in synthesis, timing/power analysis, and FPGA/silicon bring-up, ensuring that the designs meet the required specifications. Additionally, you will be involved in test plan and coverage analysis for block and SOC-level verification, collaborating with multi-disciplined and multi-site teams to achieve project goals.
What we offer
At Google, you will be part of a dynamic team that values innovation and collaboration. We encourage you to apply even if your experience doesn't match every requirement, as we believe diverse teams build better products. You will have the opportunity to work on cutting-edge technology that impacts millions of users, with a focus on delivering high-quality solutions. We offer competitive compensation and benefits, fostering a culture of growth and development within the organization.
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