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Key Highlights

  • Over 100,000 employees globally
  • Headquartered in Mountain View, California
  • Parent company Alphabet Inc. valued at $1.5 trillion
  • Google Cloud Platform serves millions of customers

Google LLC, headquartered in Mountain View, California, is a global leader in internet-related services and products, including its flagship search engine, Google Search, and the Android operating system. With over 100,000 employees, Google also offers cloud computing services through Google Cloud P...

🎁 Benefits

Google offers competitive salaries, equity options, generous PTO policies, comprehensive health benefits, and a remote work policy that allows flexibi...

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Google is known for its engineering-first culture, emphasizing innovation and collaboration. The company fosters a unique environment that encourages ...

Google

Hardware Engineer Senior

GoogleMountain View - On-Site

Posted 2w ago🏛️ On-SiteSeniorHardware Engineer📍 Mountain View💰 $156,000 - $229,000 / yearly
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Skills & Technologies

Overview

Google is hiring a Senior Silicon Package Design Engineer to design chip package substrates and contribute to innovative silicon solutions. You'll work with technologies like Cadence APD and Mentor Expedition, requiring 5 years of experience in the field.

Job Description

Who you are

You have a Bachelor's degree in Mechanical, Material, Electrical Engineering, Technology, Science, or a related field, along with 5 years of experience in chip package substrate design using Cadence APD (Allegro Package Designer) or Mentor Expedition. Your expertise includes chip package substrate layout, design rules verification, and design for manufacturing (DFM), ensuring successful tape-outs for production. You are familiar with mobile SOC package design technologies such as FCCSP, Package on Package (PoP), InFO, RDL, IPD, and 2.5D/3D Chiplet designs.

You may also hold a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture. Your experience extends to package outline, routing strategy, bump and ball grid array (BGA) assignment, and netlist management. You have a strong background in developing physical verification flows, including Layout Versus Schematic (LVS) and Design Rule Checking (DRC), and are proficient in CAD for creating mechanical drawings like Package Outline Drawings (POD).

What you'll do

As a Senior Silicon Package Design Engineer at Google, you will be part of a team that pushes boundaries in developing custom silicon solutions for Google's direct-to-consumer products. Your role will involve refining and optimizing product package architecture and design, collaborating closely with integrity (SI)/Power Integrity (PI), Test, New Product Introduction (NPI), and Mechanical Engineering teams. You will develop, implement, and debug package design methodologies and CAD flows, ensuring that package designs meet high-volume manufacturing requirements.

You will interface with packaging suppliers to ensure that package design and Bill of Materials (BOM) documentation align with production needs. Your contributions will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. You will be responsible for innovating packaging technologies and new silicon interfaces, ensuring that your designs meet the highest standards of quality and performance.

What we offer

At Google, you will have the opportunity to work on cutting-edge technologies that impact millions of users worldwide. We encourage you to apply even if your experience doesn't match every requirement, as we value diverse perspectives and backgrounds. Join us in shaping the future of technology and making a difference in the world.

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