Google

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🏢 Tech👥 100K+📅 Founded 1998📍 Mountain View, California, United States

Key Highlights

  • Over 100,000 employees globally
  • Headquartered in Mountain View, California
  • Parent company Alphabet Inc. valued at $1.5 trillion
  • Google Cloud Platform serves millions of customers

Google LLC, headquartered in Mountain View, California, is a global leader in internet-related services and products, including its flagship search engine, Google Search, and the Android operating system. With over 100,000 employees, Google also offers cloud computing services through Google Cloud P...

🎁 Benefits

Google offers competitive salaries, equity options, generous PTO policies, comprehensive health benefits, and a remote work policy that allows flexibi...

🌟 Culture

Google is known for its engineering-first culture, emphasizing innovation and collaboration. The company fosters a unique environment that encourages ...

Skills & Technologies

Overview

Google is hiring a Design Technology Co-Optimization Engineer to shape the future of AI/ML hardware acceleration. You'll work with advanced physical design methodologies and tools, focusing on cutting-edge TPU technology. This position requires 2 years of experience in Physical Design or Technology Development.

Job Description

Who you are

You hold a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or have equivalent practical experience. With at least 2 years of experience in Physical Design (RTL-to-GDS) or Technology Development, you have a strong focus on advanced nodes such as 7nm and 5nm. Your expertise includes industry-standard Place and Route (P&R) tools and Static Timing Analysis (STA) tools, along with a solid understanding of CMOS device physics and FinFET/nanosheet architectures.

You are skilled in scripting and automation using Tcl and Python (or Perl), which you utilize to manage design sweeps and data extraction effectively. A Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture, is preferred. You have experience in Design Technology Co-Optimization (DTCO), including standard cell library characterization and metal stack optimization, which enhances your ability to evaluate scaling boosters.

What you'll do

In this role, you will work to shape the future of AI/ML hardware acceleration by driving cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding applications. You will develop automated physical design methodologies and flows to accelerate technology pathfinding and enable rapid what-if analysis of emerging transistor architectures. Your contributions will influence System Technology Co-Optimization by partnering with Hardware Architects and Circuit Designers to translate process-level innovations into system-level performance gains.

You will be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. Your work will involve collaborating closely with cross-functional teams to ensure that design methodologies align with the latest technological advancements. You will also be responsible for interpreting Design Rule Manuals (DRM) to guide physical implementation, ensuring that all designs meet industry standards and performance metrics.

What we offer

At Google, you will have the opportunity to work on innovative projects that impact millions of users worldwide. We foster a collaborative environment where your ideas can flourish, and you will be encouraged to push the limits of technology. We offer competitive compensation and benefits, along with opportunities for professional growth and development within the company. Join us in shaping the future of technology and making a difference in the world.

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