Hardware Engineer • Mid-Level

Who you are

You have a strong background in hardware engineering with a focus on CPU design, particularly in Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and Static Timing Analysis (STA). Your experience includes developing and maintaining sign-offs for CPU designs, ensuring that all constraints are met effectively. You are skilled in System Verilog and understand the importance of assertions in supporting design methodologies. You have a collaborative mindset, working closely with RTL and DV teams to identify and resolve issues related to CDC and RDC. Your ability to educate team members on these topics is a key strength, as you emphasize the importance of structurally safe solutions.

What you'll do

In this role, you will be responsible for analyzing CPU designs and driving improvements in CDC and RDC methodologies. You will develop and enhance key STA checks, ensuring that all CPU designs meet the necessary timing requirements. Collaborating with RTL teams, you will recommend System Verilog assertions that support the constraints and assumptions of your designs. You will highlight any issues related to CDC and RDC, providing solutions and educating your colleagues on best practices. Your contributions will play a crucial role in maintaining the integrity and performance of Apple's CPU designs across multiple sites.

What we offer

At Apple, you will be part of a team that values innovation and excellence. We offer a collaborative work environment where your ideas can flourish. You will have the opportunity to work on groundbreaking technologies that impact millions of users worldwide. Our commitment to diversity and inclusion ensures that all voices are heard and valued. We encourage you to apply even if your experience doesn't match every requirement, as we believe in fostering talent and growth within our teams.