Tech Jobs

Apple • Beaverton - On-Site

Apple is hiring a Physical Design Engineer to contribute to high-performance PHY designs. You'll work with CAD, timing, and logic design teams to deliver outstanding designs. This role requires experience in physical design from RTL to GDSII.

Apple • Cupertino - On-Site

Apple is hiring a Physical Design Engineer to contribute to high-performance PHY design from RTL to GDSII delivery. You'll work with CAD, timing, and logic design teams to ensure outstanding PHY designs. This role requires experience in physical design methodologies and tools.

Apple • Cupertino - On-Site

Apple is hiring a Physical Design Engineer to contribute to high-performance PHY designs from RTL to GDSII delivery. You'll work with CAD, timing, and logic design teams in Cupertino. This role requires expertise in physical design methodologies and static timing analysis.

Apple • Beaverton - On-Site

Apple is hiring a Physical Design Engineer to contribute to high-performance PHY design from RTL to GDSII delivery. You'll work with CAD, timing, and logic design teams in Beaverton, Oregon.

Apple • Cupertino - On-Site

Apple is hiring a Physical Design Engineer to contribute to high-performance PHY designs from RTL to GDSII delivery. You'll work with CAD, timing, and logic design teams in Cupertino. This role requires expertise in physical design methodologies.

Apple • Cupertino - On-Site

Apple is hiring a Physical Design Engineer to contribute to high-performance PHY designs from RTL to GDSII delivery. You'll work with CAD, timing, and logic design teams in Cupertino. This role requires expertise in physical design methodologies and static timing analysis.

Apple • Cupertino - On-Site

Apple is hiring a Physical Design Engineer to contribute to high-performance PHY designs from RTL to GDSII delivery. You'll work with CAD, timing, and logic design teams to ensure outstanding physical designs. This role requires experience in physical design methodologies and tools.

Apple • Cupertino - On-Site

Apple is hiring a Physical Design Engineer to contribute to high-performance PHY designs from RTL to GDSII delivery. You'll work with CAD, timing, and logic design teams in Cupertino. This role requires expertise in physical design methodologies.

Google • Taipei - On-Site

Google is hiring a Senior Silicon Bring Up and Test Manager to lead the development of custom silicon solutions. You'll work with ASIC and SoC design, utilizing EDA tools and DFT techniques. This position requires 8 years of experience in the field.

Google • Sunnyvale - On-Site

Google is hiring a Senior ASIC Physical Design Engineer to shape the future of AI/ML hardware acceleration. You'll work on cutting-edge TPU technology and collaborate with various teams to drive physical design from RTL to GDSII. This position requires 7 years of experience in physical design and scripting skills in Python, Tcl, or Perl.

Google • Bengaluru - On-Site

Google is hiring a SoC Physical Design Lead to drive cutting-edge TPU technology for AI/ML applications. You'll leverage your expertise in ASIC design and physical implementation to lead teams and ensure successful silicon delivery. This role requires 8+ years of experience in ASIC development and management.

Google • Sunnyvale - On-Site

Google is hiring a Senior DFT Static Timing Analysis Engineer to drive cutting-edge TPU technology and ensure successful timing closure. You'll work with EDA tools and static timing analysis methodologies. This position requires 5+ years of experience in static timing and DFT architectures.

Apple • Munich - On-Site

Apple is hiring a SOC Physical Design Engineer to manage the physical design cycle from netlist to tape-out. You'll work with technologies like power and noise analysis, static timing closure, and layout verification. This position requires a strong background in deep sub-micron technology.

Google • Sunnyvale - On-Site

Google is seeking a Physical Design Engineer, University Graduate, PhD to contribute to the design and closure of custom silicon solutions for AI/ML hardware acceleration. You'll work with technologies like Python, Verilog, and various physical design principles. This entry-level position is based in Sunnyvale, CA.

Apple • Santa Clara - On-Site

Apple is hiring a CPU CDC/STA Engineer to analyze design and drive fixes for CPU constraints and methodologies. You'll work with System Verilog and Static Timing Analysis in Santa Clara.

Apple • Santa Clara - On-Site

Apple is hiring a CPU CDC/STA Engineer to analyze design and drive improvements in CPU methodologies. You'll work with System Verilog and Static Timing Analysis in Santa Clara.

Apple • Beaverton - On-Site

Apple is hiring a CPU CDC/RDC/STA Engineer to analyze design and drive fixes for CPU constraints. You'll work with System Verilog and collaborate with RTL and DV teams. This position requires experience in static timing analysis and domain crossing methodologies.

Apple • Beaverton - On-Site

Apple is hiring a Senior CPU Design Timing Engineer to drive timing closure for CPU projects. You'll work with static timing analysis tools like PrimeTime and Tempus, focusing on timing analysis and noise management. This role requires 10+ years of relevant experience.

Apple • Beaverton - On-Site

Apple is hiring a Senior CPU Design Timing Engineer to drive timing closure for CPU projects. You'll work with static timing analysis tools like PrimeTime and Tempus, focusing on timing analysis across multiple clock and power domains. This position requires 10+ years of relevant experience.

Apple • San Diego - On-Site

Apple is hiring a Senior ASIC Engineer to work on cutting-edge 5G modem platforms. You'll be responsible for timing analysis and closure in complex SoC designs. This position requires 10+ years of relevant industry experience.

Apple • San Diego - On-Site

Apple is hiring a Cellular SoC Static Timing Analysis Engineer to work on innovative 5G modem platforms. You'll be responsible for timing analysis and closure in chip design, ensuring high performance and energy efficiency. This role requires 3+ years of relevant industry experience.

Apple • San Diego - On-Site

Apple is hiring a Cellular SoC Static Timing Analysis Engineer to work on innovative 5G modem platforms. You'll be responsible for timing analysis and closure in chip design, requiring expertise in ASIC and SoC technologies.

Apple • Santa Clara - On-Site

Apple is hiring a CPU Design Timing Engineer to drive timing closure for CPU projects. You'll collaborate with CAD teams and micro-architects, utilizing skills in TCL, Python, and static timing analysis. This position requires 3+ years of relevant experience.

Apple • Beaverton - On-Site

Apple is hiring an Analog Mixed Signal IP Integration Engineer to support the integration of third-party IP in SOCs. You'll work closely with cross-functional teams and external vendors to ensure high-quality standards. This role requires 7+ years of industry experience.