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Found 4 jobs

Google • Sunnyvale - On-Site

Google is seeking a Physical Design Engineer, University Graduate, PhD to contribute to the design and closure of custom silicon solutions for AI/ML hardware acceleration. You'll work with technologies like Python, Verilog, and various physical design principles. This entry-level position is based in Sunnyvale, CA.

Python Tcl Perl Verilog Static timing analysis Clock domain crossing+3

1 month ago$132K - $189K

Hardware Engineer

Apple • Santa Clara - On-Site

Apple is hiring a CPU CDC/STA Engineer to analyze design and drive fixes for CPU constraints and methodologies. You'll work with System Verilog and Static Timing Analysis in Santa Clara.

System verilog Static timing analysis Clock domain crossing Reset domain crossing

2 months ago

Cpu Engineer

Apple • Santa Clara - On-Site

Apple is hiring a CPU CDC/STA Engineer to analyze design and drive improvements in CPU methodologies. You'll work with System Verilog and Static Timing Analysis in Santa Clara.

System verilog Static timing analysis Clock domain crossing Reset domain crossing

2 months ago

Hardware Engineer

Apple • Beaverton - On-Site

Apple is hiring a CPU CDC/RDC/STA Engineer to analyze design and drive fixes for CPU constraints. You'll work with System Verilog and collaborate with RTL and DV teams. This position requires experience in static timing analysis and domain crossing methodologies.

System verilog Static timing analysis Clock domain crossing Reset domain crossing

2 months ago

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