Design Verification Engineer • Mid-Level

Who you are

You hold a Bachelor's degree in electrical engineering or have equivalent practical experience, and you bring at least 4 years of experience working with design networking, particularly in areas like remote direct memory access (RDMA) or packet processing. Your understanding of system design principles for low latency, throughput, security, and reliability is well-established, and you have experience creating and using verification components and environments in standard verification methodology. You are familiar with verifying digital systems using standard internet protocol (IP) components or interconnects, such as microprocessor cores and hierarchical memory subsystems. Your background includes experience with transmission control protocol (TCP), IP, ethernet, PCIE, and dynamic random-access memory (DRAM), as well as network on chip (NoC) principles and protocols. You have a strong grasp of performance estimation through analysis, modeling, and network simulation, which aids you in defining and driving performance test plans. Your expertise extends to verification techniques and the full verification lifecycle, particularly in the context of ASICs and ASIC components. You are excited about being part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products.

Desirable

Experience with verification techniques and the full verification lifecycle is a plus, as is familiarity with performance verification of ASICs and ASIC components. Knowledge of ASIC standard interfaces and memory system architecture will also be beneficial in this role.

What you'll do

In this role, you will work as part of a research and development team, building verification components and environments using SystemVerilog. You will also formally verify designs with strategic value add (SVA) and industry-leading formal tools. Your responsibilities will include identifying and writing all types of coverage measures for stimulus and corner cases, as well as debugging tests with design engineers to ensure functionally correct design blocks. You will be tasked with closing coverage measures to identify verification holes and to demonstrate progress towards tape-out. Your contributions will directly impact the innovation behind products loved by millions worldwide, shaping the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration.

What we offer

At Google, you will be part of a collaborative environment that encourages innovation and creativity. You will have the opportunity to work on cutting-edge technology that influences the future of networking solutions. We value diverse perspectives and encourage you to apply even if your experience doesn't match every requirement. Join us in shaping the future of technology and making a difference in the lives of users around the globe.