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  • Over 100,000 employees globally
  • Headquartered in Mountain View, California
  • Parent company Alphabet Inc. valued at $1.5 trillion
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Google LLC, headquartered in Mountain View, California, is a global leader in internet-related services and products, including its flagship search engine, Google Search, and the Android operating system. With over 100,000 employees, Google also offers cloud computing services through Google Cloud P...

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Google

Hardware Engineer Entry-Level

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Skills & Technologies

Overview

Google is hiring a Silicon RTL Design Engineer to shape the future of AI/ML hardware acceleration. You'll work with programming languages and design tools to drive Tensor Processing Unit (TPU) technology. This position requires a PhD in a relevant field and experience in silicon engineering.

Job Description

Who you are

You hold a PhD in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, or a related technical field, and you have a strong foundation in programming languages such as C++, Python, and Verilog. Your experience includes working with Synopsys and Cadence tools, and you have a keen understanding of accelerator architectures and data center workloads. You are eager to apply your knowledge in a practical setting and contribute to cutting-edge technology.

You have at least 2 years of experience in Silicon engineering post-PhD, which has equipped you with insights into performance modeling tools and design techniques. Your knowledge extends to arithmetic units, bus architectures, accelerators, and memory hierarchies, making you well-prepared for the challenges of this role. You are familiar with high-performance and low-power design techniques, which are crucial for developing efficient hardware solutions.

What you'll do

In this role, you will collaborate with hardware and software architects and designers to architect, model, analyze, define, and design next-generation Tensor Processing Units (TPUs). Your responsibilities will include shaping the future of AI/ML hardware acceleration, driving the development of TPU technology that supports Google's most demanding applications. You will engage in product definition, design, and implementation, working closely with engineering teams to balance performance, power, features, schedule, and cost.

You will also investigate, validate, and optimize design for test (DFT) strategies, post-silicon testing, and debug processes, contributing to the advancement of silicon bring-up and qualification. Your role will involve using AI techniques to enhance physical design convergence, timing, floor planning, power grid, and clock tree design. You will play a key part in ensuring that the hardware you help design meets the rigorous demands of modern AI applications.

What we offer

At Google, you will be part of a team that is dedicated to pushing the boundaries of technology. We offer a collaborative environment where you can grow your skills and make a significant impact on the future of AI/ML hardware. You will have access to state-of-the-art resources and the opportunity to work alongside some of the brightest minds in the industry. We encourage you to apply even if your experience doesn't match every requirement, as we value diverse perspectives and backgrounds.

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