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- Over 100,000 employees globally
- Headquartered in Mountain View, California
- Parent company Alphabet Inc. valued at $1.5 trillion
- Google Cloud Platform serves millions of customers
Google LLC, headquartered in Mountain View, California, is a global leader in internet-related services and products, including its flagship search engine, Google Search, and the Android operating system. With over 100,000 employees, Google also offers cloud computing services through Google Cloud P...
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Google offers competitive salaries, equity options, generous PTO policies, comprehensive health benefits, and a remote work policy that allows flexibi...
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Overview
Google is hiring a Chip Package Signal and Power Integrity Lead Engineer to drive innovative methodologies for advanced package technologies. You'll work with tools like HFSS and MATLAB, focusing on high-speed interconnects and chip/package design. This position requires 8 years of experience in SI/PI design.
Job Description
Who you are
You have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. With 8 years of experience in signal integrity and power integrity design for chip/package or system PCB, you are well-versed in industry SIPI modeling tool chains such as HFSS, ADS, Sigrity, and Siwave. Your advanced knowledge in 2.5D/3D package design, including silicon interposer and die stacking technologies, positions you as an expert in SI/PI analysis for high-speed interconnects like HBMx, D2D, Ethernet, and PCIe.
You possess a Master's degree or PhD in Electrical Engineering or Signal/Power Integrity, which enhances your understanding of next-generation memory and chiplet standards. Your expertise includes timing budget and design methodologies, as well as a solid grasp of STA, on-chip DVD/EMIR, system voltage budgets, and VR modeling and design. You are recognized for your excellent cross-functional leadership skills and your ability to collaborate effectively with diverse teams.
What you'll do
In this role, you will shape the future of AI/ML hardware acceleration by driving the development of cutting-edge TPU technology that powers Google's most demanding applications. You will evaluate high-speed interface IP and provide critical feedback on chip floorplans to ensure optimal package/system routability and signal integrity. Leading the development of innovative methodologies for advanced package technologies, you will ensure smooth implementation from early planning through high-volume manufacturing and failure debug. Your contributions will directly impact the design and verification of complex digital designs, focusing specifically on TPU architecture and balancing performance with DFM for successful production closure.
What we offer
At Google, you will be part of a team that pushes boundaries and develops custom silicon solutions that power the future of technology. We encourage you to apply even if your experience doesn't match every requirement, as we value diverse perspectives and backgrounds. You will have the opportunity to work in a collaborative environment that fosters innovation and creativity, contributing to products loved by millions worldwide. We offer competitive compensation and benefits, along with a culture that supports professional growth and development.
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