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  • Headquartered in Mountain View, California
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Google LLC, headquartered in Mountain View, California, is a global leader in internet-related services and products, including its flagship search engine, Google Search, and the Android operating system. With over 100,000 employees, Google also offers cloud computing services through Google Cloud P...

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Google

Hardware Engineer Senior

GoogleSunnyvale - On-Site

Posted 1w ago🏛️ On-SiteSeniorHardware Engineer📍 Sunnyvale💰 $156,000 - $229,000 / yearly
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Overview

Google is hiring a Senior ASIC Physical Design Engineer to shape the future of AI/ML hardware acceleration. You'll work on cutting-edge TPU technology and collaborate with various teams to drive physical design from RTL to GDSII. This position requires 7 years of experience in physical design and scripting skills in Python, Tcl, or Perl.

Job Description

Who you are

You have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. With 7 years of experience in physical design, you are well-versed in the entire process from RTL to GDSII, including critical stages like floorplanning, place and route, and timing closure. Your scripting skills in Python, Tcl, or Perl enable you to automate and optimize design processes effectively.

You have experience working with external partners on Physical Design (PD) closure and possess a solid understanding of Static Timing Analysis (STA). You know how to define timing corners, margins, and derates, which is essential for ensuring design integrity. Your familiarity with Synopsys and Cadence PnR tools, along with backend flows such as LEC, PI/SI, and DRC/LVS, makes you a valuable asset to any team.

Your understanding of Design for Testing (DFT) concepts, including Scan, MBIST, and LBIST, allows you to contribute to the testing and validation of complex designs. You are also knowledgeable about performance, power, and area (PPA) trade-offs, which are crucial in the design of efficient ASICs. You are excited about the opportunity to work on TPU technology that powers Google's most demanding AI/ML applications.

What you'll do

In this role, you will participate in the Physical Design of complex blocks and contribute to the design and closure of the full chip and individual blocks from RTL to GDS. You will collaborate with internal logic teams and both internal and external partners to achieve optimal Power/Performance Analysis (PPA). Your responsibilities will include conducting feasibility studies for new microarchitectures and optimizing runs for finished RTL.

You will work closely with RTL, DFT, Floorplan, and full-chip Signoff teams to ensure that designs meet all specifications and performance targets. Your problem-solving skills will be put to the test as you tackle technical challenges that arise during the design process. You will also have the opportunity to drive innovation in custom silicon solutions that power the future of Google's TPU, contributing to products that are loved by millions worldwide.

What we offer

At Google, you will be part of a dynamic team that pushes the boundaries of technology. We offer competitive compensation and benefits, including opportunities for professional growth and development. You will work in a collaborative environment where your contributions directly impact the future of AI/ML hardware acceleration. Join us in shaping the next generation of technology that powers Google's most demanding applications.

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