About Apple
The personal technology company redefining user experience
Key Highlights
- Market cap of $3 trillion as of 2022
- Over 1 billion active devices worldwide
- Comprehensive medical plans including mental healthcare
- Paid parental leave and gradual return-to-work program
Apple Inc. (NASDAQ: AAPL), headquartered in Cupertino, CA, is the world's most valuable company with a market capitalization of $3 trillion as of 2022. Known for its iconic products such as the iPhone, iPad, and Mac, Apple serves over 1 billion active devices globally. The company has a strong commi...
🎁 Benefits
Apple offers comprehensive medical plans covering physical and mental healthcare, paid parental leave, and a gradual return-to-work program. Employees...
🌟 Culture
Apple's culture emphasizes an obsessive focus on user experience and consumer privacy, setting it apart from competitors. The company promotes inclusi...
Overview
Apple is hiring a Senior SoC Physical Design Engineer to oversee the physical implementation of complex SOC designs. You'll collaborate with design teams and utilize your expertise in STA and timing closure. This role requires 10+ years of relevant industry experience.
Job Description
Who you are
You have over 10 years of experience in the semiconductor industry, specifically in physical design and timing analysis. Your background includes a strong understanding of static timing analysis (STA) and timing closure processes, which are crucial for ensuring the performance of complex SOC designs. You possess programming skills in Perl and TCL, enabling you to create scripts and methodologies that enhance design efficiency and accuracy. Your hands-on experience with large design STA allows you to identify and resolve timing issues effectively, ensuring that projects meet their deadlines and specifications.
You thrive in collaborative environments, working closely with design teams to debug constraints and facilitate necessary logic changes. Your ability to communicate complex technical concepts clearly makes you a valuable asset in cross-functional discussions. You are detail-oriented and have a deep analytical mindset, allowing you to conduct thorough analyses of timing paths to pinpoint key issues that could impact project outcomes.
Desirable
While your primary expertise lies in STA, familiarity with physical design best practices and methodologies is a plus. You are open to learning new tools and technologies that can further enhance your contributions to the team. Your proactive approach to problem-solving and your commitment to continuous improvement set you apart as a leader in your field.
What you'll do
In this role at Apple, you will be responsible for the physical implementation of design partitions from netlist to tapeout for highly complex SOCs. You will collaborate with design teams to understand and debug constraints, facilitating logic changes that improve timing performance. Your expertise will be instrumental in creating timing ECOs for project tapeout, ensuring that all designs meet stringent performance criteria.
You will also work closely with the Physical Design team to highlight issues and share best practices, contributing to the overall success of the project. Your responsibilities will include creating and maintaining scripts and methodologies for analysis and runs, which will streamline the design process and enhance productivity.
As part of your role, you will conduct deep analyses of timing paths to identify key issues that could affect the performance of the SOC. Implementing timing infrastructure will be a critical aspect of your work, as you strive to optimize designs for maximum efficiency and reliability. You will document your findings and help establish guidelines and specifications that will benefit future projects.
What we offer
At Apple, you will be part of a team that is dedicated to innovation and excellence. We offer a collaborative work environment where your contributions will directly impact the development of groundbreaking products. You will have access to state-of-the-art technologies and resources that will enable you to excel in your role.
We believe in fostering a culture of inclusion and diversity, where every team member's voice is valued. You will have opportunities for professional growth and development, allowing you to expand your skill set and advance your career within the company. Join us in our mission to leave the world better than we found it, and help shape the future of technology.
Interested in this role?
Apply now or save it for later. Get alerts for similar jobs at Apple.
Similar Jobs You Might Like
Based on your interests and this role
Soc Physical Design Engineer
Apple is hiring a SoC Physical Design Engineer to manage the physical implementation of design partitions for complex SOCs. You'll work with design teams to improve timing and create documentation. This position requires 3+ years of relevant industry experience.
Hardware Engineer
Apple is hiring a SoC Physical Design Engineer to manage the physical implementation of complex SOC designs. You'll work closely with design teams to improve timing and create documentation. This role requires 3+ years of relevant experience and programming skills in Perl and TCL.
Soc Physical Design Engineer
Apple is hiring a SoC Physical Design Engineer to work on the physical implementation of complex SoC designs. You'll collaborate with design teams to improve timing and create documentation. This role requires a Bachelor's degree and experience with STA.
Soc Physical Design Engineer
Apple is hiring a Senior SoC Physical Design Engineer to oversee the physical implementation of complex SOC designs. You'll work closely with design teams to improve timing and create documentation. This role requires 10+ years of relevant industry experience.
Soc Physical Design Engineer
Apple is hiring a SoC Physical Design Engineer to manage the physical implementation of design partitions for complex SOCs. You'll work with design teams to improve timing and create documentation. This position requires 3+ years of relevant industry experience.