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- Market cap of $3 trillion as of 2022
- Over 1 billion active devices worldwide
- Comprehensive medical plans including mental healthcare
- Paid parental leave and gradual return-to-work program
Apple Inc. (NASDAQ: AAPL), headquartered in Cupertino, CA, is the world's most valuable company with a market capitalization of $3 trillion as of 2022. Known for its iconic products such as the iPhone, iPad, and Mac, Apple serves over 1 billion active devices globally. The company has a strong commi...
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Apple offers comprehensive medical plans covering physical and mental healthcare, paid parental leave, and a gradual return-to-work program. Employees...
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Wireless Design Verification Engineer • Mid-Level
Skills & Technologies
Overview
Apple is hiring a Wireless Design Verification Engineer to join their wireless silicon development team. You'll be responsible for pre-silicon RTL verification of wireless MAC and its interfaces, utilizing skills in Verilog, SystemVerilog, and UVM.
Job Description
Who you are
You have a bachelor's degree in a relevant field and possess advanced knowledge of Verilog, SystemVerilog, and UVM. Your experience includes working with SystemVerilog Assertions and ASIC verification flows, where you've developed test benches and conducted constrained random testing. You are proficient in scripting languages such as Python and Perl, which you use to enhance your verification processes. Your understanding of wireless communication systems and their architecture allows you to contribute effectively to the design verification team.
What you'll do
In this role, you will be at the center of a silicon design group, responsible for the pre-silicon RTL verification of wireless MAC and its interfaces. You will collaborate with DV methodologists, designers, and communication systems engineers to develop reusable test benches and a verification environment. Your work will involve deploying the latest methodologies with metric-driven verification to ensure the highest design quality. You will also engage in continuous improvement of verification processes and methodologies, contributing to the overall success of the wireless silicon development team.
What we offer
At Apple, you will be part of a world-class vertically integrated engineering team that emphasizes energy-efficient design and innovative technologies. You will have the opportunity to work on projects that impact hundreds of millions of customers, enhancing their user experience with cutting-edge wireless products. We encourage you to apply even if your experience doesn't match every requirement, as we value diverse perspectives and backgrounds.
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Apple is hiring a Wireless Design Verification Engineer to lead pre-silicon RTL verification of wireless MAC and its interfaces. You'll work with Verilog, SystemVerilog, and UVM in California. This position requires 10+ years of relevant industry experience.
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Apple is hiring a Wireless Design Verification Engineer to join their wireless silicon development team. You'll be responsible for pre-silicon RTL verification of wireless MAC and its interfaces, utilizing skills in Verilog and SystemVerilog. This position requires a minimum of 3 years of relevant industry experience.
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Apple is hiring a Wireless Design Verification Engineer to lead pre-silicon RTL verification of wireless MAC and its interfaces. You'll work with Verilog, SystemVerilog, and UVM to ensure high design quality in wireless silicon development.
Wireless Design Verification Engineer
Apple is hiring a Wireless Design Verification Engineer to join their wireless silicon development team. You'll be responsible for pre-silicon RTL verification of wireless MAC and its interfaces, utilizing skills in Verilog, SystemVerilog, and ASIC verification flows.
Wireless Design Verification Engineer
Apple is hiring a Wireless Design Verification Engineer to join their wireless silicon development team. You'll be responsible for pre-silicon RTL verification of wireless MAC and its interfaces. This position requires 3+ years of relevant industry experience and expertise in Verilog and SystemVerilog.