Hardware Engineer • Mid-Level

Who you are

You have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, along with at least 2 years of experience in ASIC RTL design. Your expertise includes clocking, reset, and timing-critical RTL development, and you are familiar with digital clock control circuits such as clock dividers and glitch-free muxes. You have hands-on experience with SystemVerilog for creating microarchitecture specifications and synthesizable RTL, and you are skilled in using design quality tools for Clock Domain Crossing (CDC), linting, and static timing analysis.

You are proficient in Python, Tcl, or Perl for automating design tasks and data analysis, and you have a strong understanding of clock distribution challenges, including jitter, skew management, and duty-cycle distortion. Your experience includes working on high-performance ASIC design, particularly in PLL, FLL, and DLL integration, and you are knowledgeable about low-power SoC optimization techniques like Dynamic Voltage and Frequency Scaling (DVFS) and fine-grained clock gating. You are capable of leading cross-functional efforts from initial specification through silicon bring-up, ensuring that design goals are met.

Desirable

A Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture is preferred. You have 5 years of experience with high-performance ASIC design and a proven track record of implementing complex clocking solutions. Your ability to collaborate effectively with Physical Design teams and manage skew, jitter, and multi-cycle paths is a significant asset.

What you'll do

In this role, you will shape the future of AI/ML hardware acceleration by driving the development of cutting-edge TPU technology that powers Google's most demanding AI/ML applications. You will collaborate with Physical Design teams to manage skew, jitter, and multi-cycle paths, ensuring that the Clock Control Unit (CCU) meets stringent timing and area goals. You will also work closely with Design Verification and Silicon bring-up teams to create test plans for clocking corner cases and root-cause issues in simulation and emulation.

Your responsibilities will include developing and optimizing RTL designs, ensuring that they meet performance and power requirements. You will be involved in the entire design process, from initial specifications to final silicon validation, and you will have the opportunity to influence the design direction of future TPU architectures. You will also mentor junior engineers and contribute to a collaborative team environment that fosters innovation and excellence.

What we offer

At Google, you will be part of a dynamic team that is at the forefront of technology innovation. We offer competitive compensation and benefits, including opportunities for professional development and growth. You will work in a supportive environment that values diversity and encourages collaboration across teams. Join us to make a significant impact in the field of AI/ML hardware design and contribute to projects that shape the future of technology.