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Overview
Google is hiring an RTL Design Engineer to work on Cloud TPU technology. You'll design and debug ASIC RTL using SystemVerilog or Verilog, and collaborate with physical design teams. This position requires experience in ASIC design and scripting languages.
Job Description
Who you are
You hold a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, and you have practical experience in ASIC RTL design using SystemVerilog or Verilog. You are proficient in scripting languages such as Python, Tcl, or Perl, and have experience debugging with tools like Verdi or VCS. Your knowledge extends to SoC bus protocols like APB, AHB, or AXI, and you understand register-mapped architectures.
With at least 2 years of experience in ASIC design, you have worked on management and controllability subsystems or SoC chassis logic, including resets, clocking, fuse, or security. You have collaborated with physical design teams to resolve congestion or timing issues in high-density control blocks. Your foundation in digital design fundamentals includes state machines, clock domain crossing (CDC), and reset synchronization, along with low-power design techniques.
You are familiar with sideband protocols such as I2C or SPI and have a solid understanding of hardware-software interface (HSI) design. You are eager to shape the future of AI/ML hardware acceleration and contribute to the innovation behind Google's TPU technology.
Desirable
A Master's degree or PhD in Electrical Engineering or Computer Engineering, with an emphasis on computer architecture, is preferred.
What you'll do
In this role, you will drive the development of cutting-edge TPU technology that powers Google's most demanding AI/ML applications. You will work closely with design verification (DV) teams to create comprehensive test plans and drive the resolution of functional issues in simulation and emulation. Collaboration with physical design teams will be essential to meet timing closure, area optimization, and manufacturability requirements for control logic. You will evaluate the impact of management features on the 'always-on' power footprint and work with architects to enhance system efficiency. Your contributions will be pivotal in developing custom silicon solutions that push the boundaries of technology.
What we offer
At Google, you will be part of a team that values innovation and collaboration. You will have the opportunity to work on projects that have a significant impact on the future of technology. We encourage you to apply even if your experience doesn't match every requirement, as we believe diverse teams build better products.
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