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Google LLC, headquartered in Mountain View, California, is a global leader in internet-related services and products, including its flagship search engine, Google Search, and the Android operating system. With over 100,000 employees, Google also offers cloud computing services through Google Cloud P...

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Google

Asic Design Engineer Mid-Level

GoogleSunnyvale - On-Site

Posted 2w ago🏛️ On-SiteMid-LevelAsic Design Engineer📍 Sunnyvale💰 $132,000 - $189,000 / yearly
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Skills & Technologies

Overview

Google is hiring an ASIC Design Engineer to work on ML accelerators. You'll design and verify complex digital designs, focusing on TPU architecture. This position requires 2+ years of experience in RTL design and proficiency in Verilog or SystemVerilog.

Job Description

Who you are

You have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. With at least 2 years of experience in RTL design, you are well-versed in digital design principles, including synchronous and asynchronous logic, state machines, and bus protocols. Your expertise in Verilog or SystemVerilog allows you to develop high-quality RTL for ASIC products. You are also proficient in scripting languages such as Python or Perl, which enhances your ability to automate tasks and streamline workflows.

You may hold a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture. With 5 years of experience in silicon engineering, you have a strong background in designing high-speed digital designs and optimizing designs for Performance, Power, or Area (PPA). Your analytical skills enable you to tackle complex engineering challenges effectively.

What you'll do

In this role, you will shape the future of AI/ML hardware acceleration by driving the development of cutting-edge TPU technology that powers Google's most demanding applications. You will collaborate with design validation teams to create test plans for verifying and debugging design RTL, ensuring that the designs meet the required specifications. Your contributions will directly impact the innovation behind products that are loved by millions worldwide.

You will work closely with physical design teams to ensure that your designs meet physical requirements and achieve timing closure. As part of a dynamic team, you will develop SystemVerilog RTL to implement logic for ASIC products and create and review design microarchitecture specifications. Your role will involve leveraging your design and verification expertise to verify complex digital designs, specifically focusing on TPU architecture and its integration within AI/ML-driven systems.

What we offer

At Google, you will be part of a team that designs and builds the hardware, software, and networking technologies that power many of Google's services. You will have the opportunity to work in a collaborative environment that encourages innovation and creativity. We believe in fostering a culture of continuous learning and professional growth, providing you with the resources and support needed to excel in your career. Join us and contribute to the future of technology in a role that is both challenging and rewarding.

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