About Apple
The personal technology company redefining user experience
Key Highlights
- Market cap of $3 trillion as of 2022
- Over 1 billion active devices worldwide
- Comprehensive medical plans including mental healthcare
- Paid parental leave and gradual return-to-work program
Apple Inc. (NASDAQ: AAPL), headquartered in Cupertino, CA, is the world's most valuable company with a market capitalization of $3 trillion as of 2022. Known for its iconic products such as the iPhone, iPad, and Mac, Apple serves over 1 billion active devices globally. The company has a strong commi...
π Benefits
Apple offers comprehensive medical plans covering physical and mental healthcare, paid parental leave, and a gradual return-to-work program. Employees...
π Culture
Apple's culture emphasizes an obsessive focus on user experience and consumer privacy, setting it apart from competitors. The company promotes inclusi...
Skills & Technologies
Overview
Apple is hiring a Senior ASIC Engineer to work on cutting-edge 5G modem platforms. You'll be responsible for timing analysis and closure in complex SoC designs. This position requires 10+ years of relevant industry experience.
Job Description
Who you are
You have over 10 years of experience in the semiconductor industry, particularly in static timing analysis for ASIC designs. Your expertise in timing closure and constraints generation has been honed through years of working on complex System-on-Chip (SoC) projects. You thrive in collaborative environments, working closely with designers and multi-functional teams to resolve sophisticated timing issues. Your passion for innovation drives you to push the limits of what's feasible in chip design, particularly in the realm of 5G technologies.
You possess a strong understanding of deep sub-micron technologies and their implications for high-end mobile applications. Your analytical skills allow you to tackle timing challenges effectively, ensuring that all timing requirements are met across various conditions and modes. You are detail-oriented and committed to delivering high-quality results that contribute to the success of Appleβs products.
What you'll do
As a Senior ASIC Engineer at Apple, you will take ownership of full chip and block level timing closure throughout the entire project lifecycle. You will generate block and full chip timing constraints, ensuring that all timing requirements are met. Collaborating with designers, you will help construct and modify flows to optimize timing analysis processes. Your role will involve working closely with various multi-functional teams to resolve complex timing issues for major building blocks of Appleβs SoCs.
You will be at the forefront of innovation, contributing to the development of Appleβs first in-house 5G modem platforms. Your work will directly impact the performance and efficiency of Apple products, making them beloved by millions. You will also be responsible for timing sign-off, ensuring that all aspects of timing are thoroughly validated before product release.
What we offer
At Apple, you will be part of a world-class modem team that is dedicated to pushing the boundaries of technology. We offer a collaborative work environment where your contributions will be valued and recognized. You will have the opportunity to work on groundbreaking technologies that shape the future of connectivity. We encourage you to apply even if your experience doesn't match every requirement, as we value diverse perspectives and backgrounds. Join us in our mission to innovate and deliver industry-leading products that enhance the lives of our customers.
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