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  • Over 100,000 employees globally
  • Headquartered in Mountain View, California
  • Parent company Alphabet Inc. valued at $1.5 trillion
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Google LLC, headquartered in Mountain View, California, is a global leader in internet-related services and products, including its flagship search engine, Google Search, and the Android operating system. With over 100,000 employees, Google also offers cloud computing services through Google Cloud P...

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Google

Hardware Engineer Mid-Level

GoogleSunnyvale - On-Site

Posted 3w ago🏛️ On-SiteMid-LevelSeniorHardware Engineer📍 Sunnyvale💰 $132,000 - $189,000 / yearly
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Overview

Google is hiring a Physical Design Flow and Methodology Engineer to shape the future of AI/ML hardware acceleration. You'll work with EDA tools and scripting languages to develop methodologies for high-performance ASIC or SOC projects. This position requires 2-5 years of experience in physical design flow and methodologies.

Job Description

Who you are

You have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. With at least 2 years of experience in physical design flow and methodologies, you are familiar with EDA tools for physical design and have experience in full-chip or block-level physical design. Your scripting skills in Python, Tcl, or Perl enable you to automate and enhance design processes effectively.

You hold a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture. With 5 years of experience in physical design methodologies for high-performance ASIC or SOC projects, you have a strong background in sign-off areas such as physical verification, formal verification, extraction, low power verification, STA closure, and ECO flows. Your familiarity with 2.5D/3D IC packaging and proficiency with advanced parasitic extraction tools like STARRC set you apart.

You have a proven track record of achieving optimal Power, Performance, Area (PPA) goals in complex designs. Your ability to develop and deploy repeatable design methodologies, particularly focusing on low-power verification, showcases your commitment to innovation in the field.

What you'll do

In this role, you will work to shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology that powers Google's most demanding applications. You will collaborate with chip design teams to implement tools and methodologies for physical design in leading-edge process nodes. Your responsibilities will include architecting and implementing next-generation Physical Design EDA CAD tool workflows for ASIC development.

You will develop auditing tools, checkers, and metric dashboards based on APIs from third-party EDA tools, ensuring that the physical design of blocks and subsystems is managed end-to-end. Your contributions will directly impact the innovation behind products loved by millions worldwide, as you leverage your design and engineering expertise to push boundaries in custom silicon solutions.

What we offer

At Google, you will be part of a dynamic team that values collaboration and innovation. We encourage you to apply even if your experience doesn't match every requirement, as we believe diverse teams build better products. You will have access to resources and support to grow your career while working on projects that have a significant impact on the future of technology.

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