
About Apple
The personal technology company redefining user experience
Key Highlights
- Market cap of $3 trillion as of 2022
- Over 1 billion active devices worldwide
- Comprehensive medical plans including mental healthcare
- Paid parental leave and gradual return-to-work program
Apple Inc. (NASDAQ: AAPL), headquartered in Cupertino, CA, is the world's most valuable company with a market capitalization of $3 trillion as of 2022. Known for its iconic products such as the iPhone, iPad, and Mac, Apple serves over 1 billion active devices globally. The company has a strong commi...
🎁 Benefits
Apple offers comprehensive medical plans covering physical and mental healthcare, paid parental leave, and a gradual return-to-work program. Employees...
🌟 Culture
Apple's culture emphasizes an obsessive focus on user experience and consumer privacy, setting it apart from competitors. The company promotes inclusi...
Skills & Technologies
Overview
Apple is hiring a Physical Design Engineer to contribute to high-performance PHY designs from RTL to GDSII delivery. You'll work with CAD, timing, and logic design teams in Cupertino. This role requires expertise in physical design methodologies and static timing analysis.
Job Description
Who you are
You have a strong background in physical design engineering, with experience in crafting high-performance PHY designs from RTL to GDSII. Your expertise includes generating block and chip-level static timing constraints, and you are familiar with CAD tools and methodologies that ensure correct-by-construction designs. You thrive in collaborative environments, working closely with architecture, timing, and logic design teams to deliver outstanding results.
You possess a deep understanding of physical design processes, including full chip floor-planning, pin placement, and power grid development. Your ability to develop and validate low power clock network guidelines sets you apart, as does your experience in performing block-level place and route to meet timing, area, and power constraints. You are adept at generating and implementing ECOs to address timing, noise, and EM IR violations, ensuring that designs meet stringent performance criteria.
What you'll do
In this role, you will be at the center of a PHY design effort, contributing to all phases of physical design. You will generate static timing constraints and build full chip floor-plans, including pin placements and power grids. Your responsibilities will include developing high-performance clock network guidelines and performing block-level place and route to ensure designs meet timing, area, and power constraints. You will also run physical design verification flows at both chip and block levels, providing guidelines to fix LVS and DRC violations for other designers.
You will participate in establishing CAD and physical design methodologies, contributing to flow development for chip integration. Your work will have a critical impact on delivering outstanding PHY designs that delight millions of Apple customers. You will collaborate with cross-functional teams, ensuring that all aspects of the design process are aligned and executed effectively.
What we offer
At Apple, you will be part of a team that is dedicated to crafting products that enrich people's lives. We offer a dynamic work environment where innovation is encouraged, and your contributions will directly impact the future of our products. You will have access to cutting-edge tools and technologies, and the opportunity to work alongside some of the brightest minds in the industry. We value diversity and inclusion, and we encourage you to apply even if your experience doesn't match every requirement.
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