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Google

Hardware Engineer Senior

GoogleSunnyvale - On-Site

Posted 2w ago🏛️ On-SiteSeniorHardware Engineer📍 Sunnyvale💰 $156,000 - $229,000 / yearly
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Overview

Google is hiring a Senior Physical Design Flow and Methodology Engineer to shape the future of AI/ML hardware acceleration. You'll work with EDA tools and develop methodologies for physical design in high-performance ASIC/SoC projects. This position requires 8+ years of experience in physical design flow and methodologies.

Job Description

Who you are

You have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. With 8 years of experience in physical design flow and methodologies, you are well-versed in EDA tools for physical design such as Cadence, Synopsys, and Siemens. Your experience spans full-chip or block-level physical design, and you are proficient in scripting languages like Python, Tcl, or Perl.

You hold a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture. With 10 years of experience in physical design flow and methodologies for high-performance ASIC/SoC projects, you have a deep understanding of sign-off areas such as physical verification, formal verification, extraction, low power verification, STA closure, and ECO flows. You are skilled in achieving optimal Power, Performance, Area (PPA) goals in complex designs and have familiarity with 2.5D/3D IC packaging.

Your ability to develop and deploy repeatable design methodologies, particularly focusing on low-power verification, sets you apart. You are excited about the opportunity to drive cutting-edge TPU technology that powers Google's most demanding AI/ML applications. You thrive in collaborative environments, working closely with chip design teams to implement tools and methodologies for physical design in leading-edge process nodes.

What you'll do

In this role, you will architect and implement next-generation physical design EDA and CAD tool workflows for ASIC development. You will collaborate with chip design teams to implement tools and methodologies for physical design, ensuring that they meet the demands of leading-edge process nodes. Your responsibilities will include developing auditing tools, checkers, and metric dashboards based on APIs from third-party EDA tools. You will own the physical design of blocks and subsystems end-to-end, contributing to the innovation behind products that impact millions worldwide.

What we offer

At Google, you will be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You will have the opportunity to shape the future of AI/ML hardware acceleration, working on projects that are at the forefront of technology. We encourage you to apply even if your experience doesn't match every requirement, as we value diverse perspectives and backgrounds in our team.

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