Apple

About Apple

The personal technology company redefining user experience

🏢 Tech, Hardware👥 1001+ employees📅 Founded 1976📍 Cupertino, CA4.2
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Key Highlights

  • Market cap of $3 trillion as of 2022
  • Over 1 billion active devices worldwide
  • Comprehensive medical plans including mental healthcare
  • Paid parental leave and gradual return-to-work program

Apple Inc. (NASDAQ: AAPL), headquartered in Cupertino, CA, is the world's most valuable company with a market capitalization of $3 trillion as of 2022. Known for its iconic products such as the iPhone, iPad, and Mac, Apple serves over 1 billion active devices globally. The company has a strong commi...

🎁 Benefits

Apple offers comprehensive medical plans covering physical and mental healthcare, paid parental leave, and a gradual return-to-work program. Employees...

🌟 Culture

Apple's culture emphasizes an obsessive focus on user experience and consumer privacy, setting it apart from competitors. The company promotes inclusi...

Overview

Apple is hiring a Physical Design Engineer to contribute to high-performance PHY designs from RTL to GDSII delivery. You'll work with CAD, timing, and logic design teams in Cupertino. This role requires expertise in physical design methodologies.

Job Description

Who you are

You have a strong background in physical design engineering, with experience in crafting high-performance PHY designs from RTL to GDSII. Your expertise includes generating block and chip-level static timing constraints, ensuring that designs meet timing, area, and power constraints. You are familiar with CAD tools and methodologies, and you thrive on solving complex design challenges.

You have a proven track record of performing block-level place and route, and you are skilled at developing and validating low-power clock network guidelines. Your attention to detail ensures that you can generate and implement ECOs to address timing, noise, and EM IR violations effectively. You are also adept at running physical design verification flows and providing guidance to other designers on fixing LVS/DRC violations.

What you'll do

In this role, you will be at the center of a PHY design effort, collaborating closely with architecture, CAD, timing, and logic design teams. You will generate block and chip-level static timing constraints and build full chip floor-plans, including pin placements, partitions, and power grids. Your responsibilities will include developing high-performance low-power clock network guidelines and performing block-level place and route to meet design constraints.

You will also generate and implement ECOs to fix any timing, noise, and EM IR violations that arise during the design process. Running physical design verification flows at both the chip and block levels will be a key part of your role, as will providing guidelines to other designers to address LVS/DRC violations. You will participate in establishing CAD and physical design methodologies that promote correct-by-construction designs and assist in flow development for chip integration.

What we offer

At Apple, you will have the opportunity to work on innovative products that enrich people's lives. You will be part of a diverse team that values inclusion and collaboration. We encourage you to apply even if your experience doesn't match every requirement, as we believe in the potential of every individual to contribute to our mission. Join us in crafting the future of technology and making a meaningful impact on millions of customers worldwide.

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