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Apple • Santa Clara - On-Site
Apple is hiring an ASIC Design Engineer to develop high-performance cache controllers for mobile processing systems. You'll work on RTL design and micro-architecture analysis, requiring 3+ years of ASIC design experience.
Apple • Santa Clara - On-Site
Apple is hiring a Senior ASIC Design Engineer to develop high-performance cache controllers for mobile processing systems. You'll work with RTL design and micro-architecture, focusing on performance, power, and area analysis. This position requires 10+ years of ASIC design experience.
Apple • Santa Clara - On-Site
Apple is hiring an ASIC Design Engineer - Cache Controller to develop hardware for high-performance system on a chip (SoC) memory subsystems. You'll work with RTL and micro-architecture, focusing on cache design and performance trade-offs.