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Google

Hardware Engineer Entry-Level

GoogleSunnyvale - On-Site

Posted 1 month ago🏛️ On-SiteEntry-LevelHardware Engineer📍 Sunnyvale💰 $132,000 - $189,000 / yearly
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Overview

Google is seeking a Physical Design Engineer, University Graduate, PhD to contribute to the design and closure of custom silicon solutions for AI/ML hardware acceleration. You'll work with technologies like Python, Verilog, and various physical design principles. This entry-level position is based in Sunnyvale, CA.

Job Description

Who you are

You hold a PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, and have academic or project experience in physical design. Your background includes scripting experience with languages such as Python, Tcl, and Perl, which you have utilized in various projects. You possess a solid understanding of SoC architecture and hardware description languages like Verilog, enabling effective collaboration with logic design teams to resolve timing issues. Your knowledge extends to fundamental VLSI and physical design principles, including semiconductor device physics and transistor structures such as finfet and Gate all around. You are familiar with Static Timing Analysis (STA), Clock Domain Crossings (CDC), and have experience with clock/power distribution and analysis, RC extraction, and correlation, as well as place and route techniques. You understand the intricacies of circuit design and analysis, including standard cells, SRAMs, power, noise, and IR analysis.

Desirable

Experience with cutting-edge TPU (Tensor Processing Unit) technology is a plus, as you will have the opportunity to drive innovations that power Google's most demanding AI/ML applications. You are eager to contribute to the design and verification of complex digital designs, particularly focusing on TPU architecture and its integration within AI/ML-driven systems.

What you'll do

As a Physical Design Engineer, you will be responsible for shaping the future of AI/ML hardware acceleration. You will contribute to the design and closure of subchips and individual blocks from Register-Transfer Level to Graphic Design System (RTL2GDSII). Your role will involve collaborating with RTL/Design and Product Development teams to achieve optimal Power Performance Area (PPA). You will conduct feasibility studies for new micro-architectures and optimize runs for the best Quality of Results (QoR). Your contributions will directly impact the development of custom silicon solutions that power innovative products loved by millions worldwide.

What we offer

At Google, you will be part of a team that pushes boundaries and develops cutting-edge technology. You will have the chance to work in a collaborative environment that fosters innovation and creativity. We encourage you to apply even if your experience doesn't match every requirement, as we value diverse perspectives and backgrounds. Join us in shaping the future of technology and making a significant impact in the world of AI/ML.

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