
About Apple
The personal technology company redefining user experience
Key Highlights
- Market cap of $3 trillion as of 2022
- Over 1 billion active devices worldwide
- Comprehensive medical plans including mental healthcare
- Paid parental leave and gradual return-to-work program
Apple Inc. (NASDAQ: AAPL), headquartered in Cupertino, CA, is the world's most valuable company with a market capitalization of $3 trillion as of 2022. Known for its iconic products such as the iPhone, iPad, and Mac, Apple serves over 1 billion active devices globally. The company has a strong commi...
🎁 Benefits
Apple offers comprehensive medical plans covering physical and mental healthcare, paid parental leave, and a gradual return-to-work program. Employees...
🌟 Culture
Apple's culture emphasizes an obsessive focus on user experience and consumer privacy, setting it apart from competitors. The company promotes inclusi...
Skills & Technologies
Overview
Apple is hiring a Physical Design Engineer to contribute to high-performance PHY design from RTL to GDSII delivery. You'll work with CAD, timing, and logic design teams in Beaverton, Oregon.
Job Description
Who you are
You have a strong background in physical design engineering, with experience in all phases of high-performance PHY design from RTL to GDSII delivery. Your expertise includes generating block and chip-level static timing constraints, ensuring that designs meet timing, area, and power constraints. You are familiar with building full chip floor-plans, including pin placement, partitions, and power grids, and you have a solid understanding of low power clock network guidelines.
You are skilled in performing block-level place and route, and you have experience implementing ECOs to address timing, noise, and EM IR violations. Your knowledge extends to running physical design verification flows at both chip and block levels, and you are adept at providing guidelines to fix LVS and DRC violations for other designers. You are also involved in establishing CAD and physical design methodologies that promote correct-by-construction designs.
What you'll do
In this role, you will be at the center of a PHY design effort, collaborating closely with architecture, CAD, timing, and logic design teams. Your responsibilities will include generating static timing constraints and developing full chip floor-plans that optimize pin placement and power distribution. You will validate high-performance low power clock network guidelines and ensure that designs are optimized for timing, area, and power.
You will also be responsible for performing block-level place and route, closing designs to meet stringent constraints, and generating and implementing ECOs to resolve any timing, noise, and EM IR violations. Running physical design verification flows will be a key part of your role, as will providing guidance to other designers on fixing LVS and DRC violations. Additionally, you will participate in the establishment of CAD and physical design methodologies, contributing to the development of flows for chip integration.
What we offer
At Apple, you will have the opportunity to work on innovative products that enrich people's lives. You will be part of a diverse and inclusive team that values collaboration and creativity. We encourage you to apply even if your experience doesn't match every requirement, as we believe that diverse teams build better products. Join us in crafting the future of technology and making a meaningful impact on millions of customers worldwide.
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