Timing Design Engineer • Mid-Level

Who you are

You have a BS degree in a technical discipline and a minimum of 3 years of relevant experience in ASIC design. Your proven knowledge of timing sign-off and static timing analysis (STA) makes you a strong candidate for this role. You understand the intricacies of SoC design and have experience developing timing constraints for both regular and custom requirements. You thrive in collaborative environments, working closely with RTL designers to grasp design intent and clock structures. Your ability to innovate timing constraints and flows is essential for achieving timing closure and addressing potential issues in timing analysis.

What you'll do

As a Timing Design Engineer at Apple, you will be responsible for all aspects of timing in SoC design. Your key responsibilities will include timing sign-off and the development of STA and sign-off flows. You will own the timing constraints at both the IP and block levels, ensuring that they meet the required quality standards. You will collaborate with various teams, including RTL designers and the Physical design team, to ensure that timing is closed and signed off effectively. Your role will also involve coming up with innovative ideas and plans to verify your timing constraints, ensuring that the design meets performance expectations.

What we offer

At Apple, you will be part of a diverse team that values creativity and innovation. We offer a collaborative work environment where your ideas can flourish. You will have the opportunity to work on cutting-edge technology and contribute to products that change lives for the better. We encourage you to apply even if your experience doesn't match every requirement, as we believe in the potential of every individual to make a significant impact.