Electrical Engineer • Senior

Who you are

You have a Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience, along with 5 years of experience in SoC and DFT aspects. Your background includes hands-on experience with ATPG, Low Power designs, Memory BIST, JTAG, and IJTAG tools and flows. You are proficient in using DFT EDA Tool Tessent and have a solid understanding of synthesis, lint, LEC, and DFT timing and STA. You are also familiar with scripting languages such as Perl and Python, which you use to automate processes and improve efficiency.

With a strong grasp of high-performance design DFT techniques, you understand the end-to-end flows such as Design, Verification, DFT, and PD. You have the ability to scale DFT with a focus on area overhead, ensuring that designs meet performance and efficiency standards. You thrive in collaborative environments and enjoy working with multi-disciplined and multi-site teams to push the boundaries of silicon solutions.

Desirable

You have 10 years of experience in SoC and DFT aspects, which has equipped you with a deep understanding of the complexities involved in silicon design and validation. Your experience includes working on SOC level ATPG and MBIST pattern generation, as well as supporting post-silicon bring-up activities. You are adept at writing scripts to automate DFT flows, which enhances your team's productivity and effectiveness.

What you'll do

In this role, you will be responsible for implementing and validating SOC DFT Architecture, contributing to the development of custom silicon solutions that power Google's direct-to-consumer products. You will work on SOC level ATPG and MBIST pattern generation, ensuring that coverage goals are met and that the designs are robust and reliable. Your contributions will support post-silicon bring-up, including subsystem level pattern retargeting, which is critical for the success of the products.

You will collaborate closely with the product engineering team on silicon bring-up, integrating SOC DFT, Scan architecture, IJTAG network integration, and verification. Your role will also involve gate level simulation, both no-timing and timing, to ensure that the designs function as intended under various conditions. You will develop and release the SOC DFT STA Constraint and validation along with RTL signoff checks, ensuring that all aspects of the design meet the required specifications.

What we offer

At Google, you will be part of a team that is dedicated to innovation and excellence in silicon design. You will have the opportunity to work on cutting-edge technologies and contribute to products that are loved by millions worldwide. We encourage you to apply even if your experience doesn't match every requirement, as we value diverse perspectives and backgrounds. Join us in shaping the future of hardware experiences, delivering unparalleled performance, efficiency, and integration.