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Skills & Technologies
Overview
Google is hiring a Senior DFT Static Timing Analysis Engineer to drive cutting-edge TPU technology and ensure successful timing closure. You'll work with EDA tools and static timing analysis methodologies. This position requires 5+ years of experience in static timing and DFT architectures.
Job Description
Who you are
You have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. With 5 years of experience in static timing, you have owned full chip timing signoff, authored constraints, and verified full chip static timing analysis. Your expertise extends to DFT architectures and associated test methodologies, and you are familiar with Tessent generated DFT timing constraints, SSN bus networks, and mode merging.
You possess experience with EDA tools and EDA Tcl commands for timing analysis, timing closure, parasitic extraction, noise glitch, and crosstalk. You have developed test mode timing constraints and have a strong understanding of semiconductor device physics and SPICE simulation. Your preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture, and 10 years of experience in STA, leading test mode timing constraint development and timing convergence for SOC projects.
What you'll do
In this role, you will shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology. You will participate in both static timing analysis methodology development and support, as well as chip implementation and timing signoff execution. Your responsibilities will include developing, supporting, and executing implementation flows around industry-standard static timing and parasitic extraction tools. You will debug flow issues reported by the team and work with EDA vendors to resolve them where necessary.
You will lead one or more aspects of physical design or physical design flow/methodology, ensuring successful tape-outs and shipping silicon. You will extract design parameters, analyze QoR metrics, and identify data trends. Additionally, you will plan the clock distribution architecture for critical test modes, ensuring that all aspects of timing closure are met.
What we offer
At Google, you will have the opportunity to work with some of the brightest minds in the industry, contributing to projects that shape the future of technology. We offer a competitive salary and benefits package, along with a collaborative work environment that encourages innovation and professional growth. You will be part of a team that values diversity and inclusion, and we encourage you to apply even if your experience doesn't match every requirement.
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