Hardware Engineer • Mid-Level

Who you are

You have a BS with 4+ years, MS with 2+ years, or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development — your background includes demonstrated success in taping out complex silicon designs. You are hands-on and have a deep understanding of physical design methodologies, enabling you to deliver optimized solutions for power, performance, and area (PPA).

You thrive in collaborative environments, working closely with RTL designers to define and execute physical design strategies — your ability to analyze and optimize design for timing, power, and area trade-offs is essential. You are familiar with EDA tools and have experience collaborating with ASIC partners to drive successful implementations.

What you'll do

In this role, you will develop, build, and own tools, flows, and methodologies for physical implementation — your contributions will directly impact silicon’s performance and cost efficiency. You will own the physical implementation of floorplan blocks from floorplanning to final signoff, ensuring that all aspects of the design meet the required specifications.

You will collaborate with RTL designers to drive optimal block implementation solutions, analyzing and optimizing designs for timing, power, and area trade-offs — your expertise will help increase team productivity and execution velocity. You will also work closely with EDA vendors to ensure that the tools and methodologies you develop are effective and efficient.

What we offer

At OpenAI, you will be part of a team that is shaping the future of technology through advanced AI systems — we are committed to providing reasonable accommodations to applicants with disabilities. You will have the opportunity to work in a dynamic environment where your contributions will have a significant impact on the performance and efficiency of our silicon designs. Join us in our mission to ensure that the benefits of AI are widely shared.