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Apple • Cupertino - On-Site
Apple is hiring a SoC Power Flow Methodology Engineer to develop and enhance low-power design flows for next-generation chips. You'll work on power analysis and optimization, requiring a strong understanding of VLSI designs and SOC design flows.

Apple • Beaverton - On-Site
Apple is hiring a SoC Power Flow Methodology Engineer to develop low-power design methodologies for next-generation chips. You'll work on power analysis and optimization tools in Beaverton, Oregon.

Apple • Austin - On-Site
Apple is hiring a SoC Power Flow Methodology Engineer to develop and enhance low-power design flows for next-generation chips. You'll work with VLSI designs and power optimization techniques in Austin.

Apple • Irvine - On-Site
Apple is hiring a Senior ASIC Power Engineer to drive SoC power simulation, analysis, and optimization for next-generation wireless SOC products. You'll work on power estimation and optimization strategies, requiring deep technical expertise in power estimation.

Apple • London - On-Site
Apple is hiring a Senior RTL Power Optimisation Engineer to design and manufacture high-performance, power-efficient processors. You'll work with power analysis and optimization for GPU products, utilizing skills in simulation and data analysis.

Baidu • Sunnyvale - On-Site
Baidu is hiring a Low Power SoC Hardware Architect to design and define lower power subsystems for AI engines. You'll collaborate with a world-class team to improve power efficiency in both data center and edge SoCs. This position requires expertise in power optimization and SoC design.