Tech Jobs

Apple • Cupertino - On-Site

Apple is hiring a SoC Power Flow Methodology Engineer to develop and enhance low-power design flows for next-generation chips. You'll work on power analysis and optimization, requiring a strong understanding of VLSI designs and SOC design flows.

Apple • Beaverton - On-Site

Apple is hiring a SoC Power Flow Methodology Engineer to develop low-power design methodologies for next-generation chips. You'll work on power analysis and optimization tools in Beaverton, Oregon.

Apple • Beaverton

Apple is hiring a SoC Power Flow Methodology Engineer to develop and enhance low-power design flows for next-generation chips. You'll work on power analysis and optimization, requiring a strong understanding of VLSI designs and scripting skills.

Apple • Austin - On-Site

Apple is hiring a SoC Power Flow Methodology Engineer to develop and enhance low-power design flows for next-generation chips. You'll work with VLSI designs and power optimization techniques in Austin.

Amazon • Bengaluru - On-Site

Amazon is hiring an ASIC Engineer specializing in Physical Design to innovate on silicon IP for Echo devices. You'll work with RTL designers and drive physical design closure while collaborating with third-party services. This role requires 5+ years of experience in ASIC Physical Design.

Apple • Munich - On-Site

Apple is hiring a SOC Physical Design Engineer to manage the physical design cycle from netlist to tape-out. You'll work with technologies like power and noise analysis, static timing closure, and layout verification. This position requires a strong background in deep sub-micron technology.

Google • Sunnyvale - On-Site

Google is seeking a Physical Design Engineer, University Graduate, PhD to contribute to the design and closure of custom silicon solutions for AI/ML hardware acceleration. You'll work with technologies like Python, Verilog, and various physical design principles. This entry-level position is based in Sunnyvale, CA.

Apple • Santa Clara - On-Site

Apple is hiring a CPU Physical Design Methodology and Optimization Engineer to improve the power, performance, and area of CPU designs. You'll collaborate with various teams and apply machine learning techniques in silicon design. This role requires expertise in physical design methodologies.

Apple • Santa Clara - On-Site

Apple is hiring a CPU Physical Design Methodology and Optimization Engineer to improve the power, performance, and area of CPU designs. You'll collaborate with various teams and apply machine learning techniques in silicon design. This role requires expertise in physical design methodologies.

Apple • Austin - On-Site

Apple is hiring a GPU Energy Modeling and Analysis Engineer to develop micro-architectural level energy models and analyze power consumption in GPUs. You'll work on power reduction techniques and collaborate with various engineering teams in Austin.

Apple • Austin - On-Site

Apple is hiring a GPU Energy Modeling and Analysis Engineer to develop micro-architectural level energy models for power estimation and analysis. You'll work on power reduction techniques across the GPU stack in Austin.

Apple • Austin - On-Site

Apple is hiring a GPU Energy Modeling and Analysis Engineer to develop micro-architectural level energy models and analyze power consumption for next-generation GPUs. You'll work closely with cross-functional teams to drive power reduction techniques and improve GPU architecture. This role requires knowledge of computer architecture and experience in energy reduction across hardware and software stacks.

Apple • Santa Clara - On-Site

Apple is hiring a CPU Gate Level Synthesis Engineer to optimize design quality for high-performance CPUs. You'll work with RTL to gate level synthesis and collaborate with cross-functional teams. This position requires experience in digital design and synthesis methodologies.

Amazon • Cambridge - On-Site

Amazon is hiring a Senior ASIC Verification Engineer to join the Blink/Ring ASIC Team in Cambridge. You'll define architecture specifications, create microarchitecture specifications, and ensure quality through various verification processes. This role requires expertise in ASIC design and verification.

Apple • London - On-Site

Apple is hiring a Junior RTL Power Optimisation Engineer to design and optimise power-efficient processors and SoCs. You'll work with power analysis tools and machine learning to enhance GPU performance. This role requires a good understanding of RTL design.

Apple • London - On-Site

Apple is hiring a Senior RTL Power Optimisation Engineer to design and manufacture high-performance, power-efficient processors. You'll work with power analysis and optimization for GPU products, utilizing skills in simulation and data analysis.

Apple • Santa Clara - On-Site

Apple is hiring a CPU Gate Level Synthesis Engineer to optimize design quality for high-performance CPUs. You'll work with RTL and synthesis methodologies in Santa Clara. This position requires experience in digital design and power analysis.

Baidu • Sunnyvale - On-Site

Baidu is hiring a Principal Digital Design Engineer to design high-performance, low-power CPU architectures for cellular modems. You'll work with multi-national teams and leverage your expertise in CPU design and digital design flows. This position requires at least 5 years of relevant experience.